Existing logic verification technology is mostly based on the use of field-programmable gate arrays (FPGAs), a cluster of computers (e.g., PCs), or specially designed application-specific integrated circuit (ASIC) systems.
Current FPGA-based technologies usually try to directly map the target logic into a group of FPGAs and to emulate the target system. This approach is not scalable and becomes extremely expensive as the complexity of the target logic increases. Also, the synthesizing processes normally takes a long time, which makes this approach very inefficient at the early stages of the chip logic development when design changes occur very often. Furthermore, FPGAs are intrinsically much slower than custom designed circuits.
The biggest problem of simulating complex chip logic on a PC cluster is the low performance. The main hindering factors come from instruction and data cache locality that are not well-suited to this type of simulation, inefficient communication channels, and operating system overhead.
Some companies have developed dedicated logic simulation machines with specially designed ASICs to accelerate the logic simulation process. Those systems are usually extremely expensive to develop and upgrade, and tend to be less flexible than other types of systems. The existing machines are generally not commercially available to outside users.